1. Field of the Invention
The present invention relates to a clock recovery circuit for a quadrature amplitude modulation (QAM) demodulator in a digital microwave communication system.
2. Description of the Related Art
In a demodulator of a digital microwave communication system, a clock signal is recovered from a received signal, and the received signal is sampled by using the recovered clock signal to obtain digital data.
In a prior art clock recovery circuit (see JP-A-9-247229 & U.S. Pat. No. 5,789,988), an analog/digital (A/D) converter performs an A/D conversion upon a baseband analog signal in synchronization with a sampling clock signal having a time period half of a symbol time period. A phase detector receives successive first, second and third sampled data from the A/D converter, determines whether or not a signal transition formed by the first and third sampled data crosses a zero value within a predetermined time deviation, and compares a polarity of the second sampled data with a polarity of one of the first and third sampled data to generate a phase detection signal when the signal transition crosses the zero value. Further, a loop filter is connected to an output of the phase detector, and a voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter. This will be explained later in detail.
In the above-described prior art clock recovery circuit, however, since the A/D converter is operated by using the sampling clock signal having a time period half of the symbol clock signal, i.e., a frequency twice the modulation frequency, the operational speed of the A/D converter has to be increased, which increases the power consumption and the manufacturing cost.